Finally…

From: Jessica Stewart

Sent: Tuesday, January 06, 2009 12:54 PM

Subject: MASc Seminar Notice: Yu Wang

Department of Computing and Software – McMaster University

MASc Seminar

Candidate: Yu Wang

Title:                Sampled-data Supervisory Control

Date:                Monday, January 12^th 2009

Time:               1:00 PM

Place:               ITB  201

ABSTRACT

This thesis focuses on issues related to implementing theoretical Discrete-Event Systems (DES) supervisors, and the concurrency and timing delay issues involved.

Sampled-data (SD) supervisory control deals with timed DES (TDES) systems where the supervisors will be implemented as SD controllers.  An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes states, and updates its outputs.

In this thesis, we identify a set of existing TDES properties that will be useful to our work, but not sufficient.  We extend the TDES controllability definition to a new definition, SD controllability, which captures several new properties that will be useful in dealing with concurrency issues, as well as make it easier to translate a TDES supervisor into an SD controller.

We then establish a formal representation of an SD controller as a Moore Finite State Machine (FSM), and describe how to translate a TDES supervisor to a FSM, as well as necessary properties to be able to do so.  We discuss how to construct a single centralized controller, as well as a set of modular controllers and show that they will produce equivalent output.

Next, we capture the enablement and forcing action of a translated controller in the form of a TDES supervisory control map, and show that the closed-loop behavior of this map and the plant is the same as that of the plant and the original TDES supervisor. We also show that our method is robust with respect to nonblocking and certain variations in the actual behavior of our physical system.

We also introduce a set of predicate-based algorithms to verify the SD controllability property, as well as certain other conditions that we require.  We have created a software tool for verifying these conditions and provide the source code in the appendix.  We have implemented these algorithms using binary decision diagrams (BDD).

Finally, we discuss an application example based on a Flexible Manufacturing System.  We also presented the corresponding FSM, translated from the example’s supervisors.

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